The present invention relates generally to semiconductor integrated circuit (IC) chip designs, and more particularly to a mechanically strong seal ring structure that can limit and stop the advance of unintended cracks from the corner and edge of an IC chip.
IC chips are constructed in rectangular arrays on a round single crystal wafer. Most wafers are made of silicon. The chips are separated by scribing and breaking, stress breaking, or, most typically, sawing. The separation lines are aligned along selected crystal axes, such that the separation proceeds in an orderly and predictable manner. However, unintended stress cracks are inevitably produced by the separation processes. Such cracks are most numerous near the corners of a chip where two perpendicular separation lines meet. Such cracks also advance along crystal axes. Because of the crystal orientation that is most propitious for chip production, unintended cracks are seen to begin perpendicularly to the chip edge.
The sharp end of a crack concentrates disruptive energy that is directed to advance the crack. This is a dangerous and undesirable situation in any material. Of course, such a crack can advance unpredictably into the core circuitry of the chip and destroy it when silicon structures, dielectric layers, metal wiring layers, and other structures are disrupted. Such cracks are also conduits for the introduction of destructive contaminants.
When the chip is encapsulated in a metal, ceramic, or plastic package, further stresses that can cause cracks are produced. Once initiated, these cracks follow the same progression as those from chip separation.
When integrated circuit chips are separated by any means, there is always a possibility of initiating micro-cracks from the edges, especially near the corners. Encapsulation can also initiate cracks. By nature, cracks tend to advance. A crack that progresses into the core circuitry of an IC is likely to cause failure. A structural seal ring between the core circuitry and the edges of the IC chip is typically constructed on the chip simultaneously with the construction of the core circuitry. The intended purpose of the seal ring is to limit the intrusion of any cracks into the vital interior core circuitry. Also, the seal ring can prevent moisture penetration or chemical damage like acid, alkaline containing or diffusion of contaminating species. As critical geometries of ICs continue to grow smaller with each technology generation, the scale and distribution of inherent stresses increase, and the problem of cracks becomes more significant. To limit and stop the cracks, a seal ring structure is installed around the active face of the IC chip during production, using a combination of surface topology, and layers of dielectric and metal patterns. Each new technology generation is likely to require a new approach to seal ring designs. As such, the provision of a protective seal ring becomes more critical and complex.
In current multilevel metal assemblies, a damascene or dual damascene approach is used for producing a seal ring structure. Each layer of metallization is composed of two sublevels. The lower sublevel is an arrangement of plugs that fill etched vias in a core circuitry region. The upper sublevel is an arrangement of bridges that fill etched trenches and connect through the plugs to lower metal lines or semiconductor structures. In this kind of seal ring, the total structure is not sufficiently resistant to the intrusion of cracks, and especially weak is the sublevel plugs.
Desirable in the art of seal ring structure are designs that can better limit and stop the advance of cracks from the edge of an IC chip.